Very Large Scale Integration (VLSI) Test

Assesses knowledge of early design planning including die size estimation, macro placement, blockage definition, and pin alignment. Evaluates congestion management, row utilization, aspect ratio tuning, and legal placement strategies to ensure routability and timing integrity. Also includes budgeting for power domains and planning for hierarchical blocks.

Focuses on the structure and optimization of the clock network including H-tree, buffered trees, mesh architectures, and hybrid models. Evaluates the ability to manage skew, insertion delay, clock latency, and uncertainty. Includes handling clock gating, multi-clock domains, and strategies to meet CTS-related timing closure goals.

Tests deep knowledge of setup/hold violations, clock-to-Q delays, launch/capture paths, and clock domain crossing (CDC) challenges. Includes multi-mode multi-corner (MCMM) analysis, CRPR (clock reconvergence pessimism removal), use of timing exceptions, and advanced path analysis such as asynchronous and false paths. Also covers ECO-based timing recovery.

Evaluates awareness of crosstalk noise, glitch propagation, ground bounce, IR drop impacts, and coupling capacitance issues. Tests familiarity with physical mitigation techniques such as shielding, wire spreading, layer switching, and net ordering. Includes analytical methods for noise margin verification and guardbanding strategies.

Focuses on dynamic and leakage power reduction techniques at block and chip level. Includes clock gating, power gating, multi-threshold (multi-Vt) cells, multiple voltage domain partitioning, retention cells, and power-aware place & route. Also covers UPF/CPF methodologies, IR drop budgeting, and switching activity-driven optimizations.

Tests understanding of global and detailed routing strategies, metal stack planning, layer assignments, via resistance, and antenna effect handling. Includes resolving DRC violations such as shorts, spacing, width, and enclosure errors. Emphasizes the interaction between routing decisions and sign-off readiness, including metal fill and DFM rule compliance.

Covers scan chain insertion, scan reordering, test point insertion, boundary scan logic, and compression techniques like EDT. Includes awareness of how scan logic interacts with floorplanning, timing, and clocking. Also tests understanding of ATPG readiness, stuck-at/fault grading, and how DFT constraints impact physical implementation.

Assesses knowledge of final-stage sign-off including DRC, LVS, ERC, IR drop, EM (electromigration), and parasitic extraction (RC). Covers GDSII generation, PPA analysis, MCMM final checks, and coordination with foundry-specific tapeout rules. Emphasizes closing sign-off loops with ECOs and verifying across worst-case PVT corners.

Tests expert-level knowledge in chip-level partitioning, interface planning, hierarchical budgeting, and flow customization. Includes resonant clocking, adaptive voltage scaling (AVS), floorplan reuse across chips, and mentoring design teams. Covers evaluation of technology node impacts (e.g., 7nm, 5nm), DFM tradeoffs, and platform-wide timing/power scalability.